Method for generating minimal leakage current input vector using heuristics

ABSTRACT

A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS and NMOS parts and P and N devices of the integrated circuit into edges, selecting between PMOS and NMOS logic representations the one with deepest serial stack; and for the selected PMOS or NMOS logic representation, assigning weights to the edges, thereby generating a weighted graph. The assignment includes starting from the output terminal to the Power V dd  (for PMOS) or Ground V ss  (for NMOS), and labeling edge weights in a descending order. The resulted cost function from the method of the present invention can be applied as heuristics in different algorithms, such as branch-and-bound, simulated annealing, or genetic algorithm.

FIELD OF THE INVENTION

The present invention generally relates to integrated circuits, and morespecifically to a method for generating an input vector to reduce theleakage current in an integrated circuit by using heuristics.

BACKGROUND OF THE INVENTION

With the scaling down of integrated circuit (IC) design, the leakagecurrent imposes severe power problem for devices with IC. The powerconsumed by an integrated circuit can be categorized as dynamic, staticand current leakage, respectively. The leakage current consumes thepower and generates heat even when the circuit is not in operation;hence, minimizing the leakage current can alleviate both the powerconsumption and the heat dissipation problems.

U.S. Pat. No. 6,191,606 B1 (2001), “Method and apparatus for reducingstandby leakage current using input vector activation” disclosed amethod and an apparatus for reducing standby leakage current in CMOScircuit using selected input vectors. FIG. 1 shows the conceptual modelof how an input vector can be used to turns off part of the circuit.When a normal clock Clk1 is applied to the input register 101, an inputvector is applied to the combination logic circuit 103, which operatesto generate an output vector. When a gated clock Clk2 is applied to theinput vector, a pre-determined input vector is applied to thecombinational logic circuit 103 to turn off part of the circuit tominimize the leakage current for reducing power consumption. However,the drawback of the patent is that the pre-determined input vector mustbe manually determined by visual inspection to the given logic circuit.

U.S. Pat. No. 6,515,513 B2 (2002) disclosed a system and method forinserting leakage reduction control in logic circuits. In this patent, aprobabilistic analysis algorithm based on a user-defined probability isused to compute the input vector for leakage current reduction.

Bhunia, et al, disclosed a synthesis method for input vector computingin a paper titled “A Novel Synthesis Approach for Active Leakage PowerReduction Using Dynamic Supply Gating”, Proceeding of Design AutomationConference, June 2005. FIG. 2 shows a conceptual view of gating the idlecircuitries in a combinational logic circuit in an active mode to reducethe leakage current. The disclosed algorithm employs a logic synthesisapproach based on Shannon expansion to find idle circuitries in anactive mode. As shown in FIG. 2, during an active mode, there exist idlecircuitries in a functional block, thus gating these idle circuitries toreduce leakage current. Once the idle circuitries and associated inputvectors are determined, a gated clock can be applied to control aregister to provide an input vector to the pre-determined circuitries.This method is applicable to logic circuit in an active mode.

The leakage current of a TSMC 0.13 um CMOS 4-input NOR gate with respectto different inputs is measured and found to have the differencesbetween maximum and minimum leakage currents of an order of two. Anotherobservation is that the closer the off-state devices are to the outputterminal, the lower the leakage current is. This phenomenon implies thatan optimization factor based on the above observation can be used as aheuristic design to compute an optimal input vector for minimizingleakage current.

SUMMARY OF THE INVENTION

The present invention has been made to overcome the above-mentioneddrawback of conventional leakage current reduction techniques. Theprimary object of the present invention is to provide a method forgenerating an input vector to integrated circuits so as to minimize theleakage current.

To achieve the above objects, the present invention provides a methodusing greedy heuristics with output terminal biased off-state stackingdevice as the optimization factor to generate an input vector tointegrated circuits for minimizing the leakage current. The methodincludes the following steps of: (a) transforming an integrated circuitto a logic representation with PMOS and NMOS parts, and P and N devicesof the integrated circuit into edges; (b) selecting between PMOS andNMOS logic representations the one with deepest serial stack; and (c)for the selected PMOS or NMOS logic representation, assigning weights tothe edges, the assignment including starting from the output terminal tothe Power V_(dd) (for PMOS) or Ground V_(ss) (for NMOS), and labelingedge weights in a descending order. The resulted cost function from themethod of the present invention can be applied as heuristics indifferent algorithms, such as branch-and-bound, simulated annealing, orgenetic algorithm.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become better understood from a careful readingof a detailed description provided herein below with appropriatereference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic view of a gated input using the gated clock tothe input register.

FIG. 2 shows a schematic view of gating idle circuit block in activemode.

FIG. 3A shows a flowchart illustrating the method of the presentinvention.

FIG. 3B shows a flow diagram illustrating the second step in FIG. 3A.

FIG. 4A shows a PMOS and NMOS logic representation diagram of an exampleCMOS circuit.

FIG. 4B shows a weighted graph WF with two sub-graphs WFP and WFN forthe example logic representation in FIG. 4A.

FIG. 4C shows weight assignment to sub-graph WFP of FIG. 4B.

FIG. 4D shows a computed result for the example in FIG. 4A using thepresent invention and a branch-and-bound algorithm.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 3A shows a flowchart illustrating the method for generating inputvector for minimizing the leakage current of the present invention.Referring to FIG. 3A, step 301 is to transform an integrated circuit,for example a CMOS circuit, into a logic representation with PMOS andNMOS parts. To more understand the operation of step 301, consider thefollowing detailed description. For a given CMOS circuit, V_(dd),V_(ss), output terminals and all wire connection points are transformedinto nodes, and P and N devices of the given CMOS circuit aretransformed into edges. To simplify the graph, only one node is used torepresent connected edges. For example, if there are 10 devices directlyconnected to an output terminal, only one node is used to represent theoutput terminal. The transformed weighted graph is called WF, includingtwo sub-graphs called, WFP (for PMOS) and WFN (for NMOS), respectively.

Step 302 in FIG. 3A is to select between the PMOS and the NMOS logicrepresentations the one with deepest serial stack. The operation of step302 is shown in FIG. 3 b and further described as follows. Referring toFIG. 3 b, the depths of the two sub-graphs WFP and WFN are firstdetermined, respectively, as shown in step 302 a. By performing adepth-first search (DFS) algorithm from the output terminal node to thePower V_(dd) and Ground V_(ss) to find the longest path with most edges,i.e., the depth, traversed in each sub-graph. Step 302 b is to determinewhether the depth of sub-graph WFP is greater than or equals to thedepth of sub-graph WFN. If so, the sub-graph WFP is used as for thefollowing weight assignment step, as illustrated in step 302 c, i.e.WF_(T)=WFP. Otherwise, WFN is used, as illustrated in step 302 d, i.e.WF_(T)=WFN. In other words, WF_(T) is the maximum of WFP and WFN.

It is worth noticing that in the case of equal depth for bothsub-graphs, either WFP or WFN can be used for weight assignmentcomputation. However, because PMOS provides a better leakage control ingeneral, sub-graph WFP is usually selected when both sub-graphs haveequal depth. However, if different manufacturing process is used so thatNMOS provides a better leakage control, the sub-graph WFN can beselected for weight assignment.

Referring back to FIG. 3A, on the PMOS or NMOS selected in step 302,step 303 is to assign weights to the edges, start from the outputterminal to the Power V_(dd) (PMOS) or Ground V_(SS) (NMOS), and labeledge weights in a descending fashion. The operation of step 303 isfurther described as follows. A depth-first search (DFS) orbreadth-first search (BFS) algorithm is performed to the selectedsub-graph to assign a weight to each edge. The assignment starts fromthe output terminal with the heaviest weight towards Power V_(dd) orGround V_(ss) in a non-decreasing order. The weight assigned to eachedge is not limited any specific value as long as they form anon-increasing sequence as they move towards Power V_(dd) or GroundV_(ss). In general a decreasing sequence is preferred; however, if thedepth is large, for example, deeper than 10, a non-increasing order cansimplify the computation.

Based on the weighted graph generated in the above step 303, aheuristics is selected to find an input vector which creates a maximalweight sum. The heuristics is only for algorithm realization, and notlimited to any specific type, such as branch-and-bound, simulatedannealing, and genetic algorithm.

FIGS. 4A-4D shows an example of using the method of the presentinvention to determine an input vector for a CMOS circuit. FIG. 4A showsthe PMOS and NMOS logic representations of the CMOS circuit. FIG. 4Bshows the weighted graph WF generated by applying the step 301 of FIG.3A to transform the PMOS/NMOS logic representation into WFP and WFN,respectively. It is worth noticing that the depth of WFP is four and thedepth of WFN is 3. Therefore, the sub-graph WFP is used for thefollowing weight assignment.

FIG. 4C shows the weight assigned to each edge in the sub-graph WFP . Inthe left figure of FIG. 4C, the weight assignment starts with outputterminal V4, and moves towards V1 (V_(dd)). On each edge visited, theheaviest weight is assigned to the ones closest to V4, and decreased theweight further away from V4. As aforementioned, the weights are limitedto any specific value as long as they form a non-increasing sequence. Inthis process, an edge may have more than one weight assignment, forexample, P1, P4, P6, P8 and P9. Under these circumstances, the heaviestweight assignment is used and the final weight assignment is in thefigure on the right of FIG. 4C.

FIG. 4D shows the input vector with minimal leakage current computedusing a branch-and-bound algorithm using the above weighted graphgenerated in FIG. 4C. As shown in FIG. 4D, the total weight is 6.7 byassigning the values {1, 0, 1} to the input vector {A, B, C}. The figureat the bottom of FIG. 4D shows the off-state devices with respect to thecomputed input vector in black nodes. It is worth noticing that otherheuristics, such as simulated annealing or genetic algorithm can be usedto compute the input vector with the minimal leakage current. The inputvector is thus used as the input for the gating logic to feed into thecircuitry as the gated input.

From the above description, it can be seen that this invention usesgreedy heuristics with output terminal biased off-state stacking deviceas the optimization factor and quickly generates the input vector tointegrated circuits for minimizing the leakage current. The resultedcost function from the method of the present invention can be applied asheuristics in different algorithms, such as branch-and-bound, simulatedannealing, genetic algorithm, etc.

Although the present invention has been described with reference to thepreferred embodiments, it will be understood that the invention is notlimited to the details described thereof. Various substitutions andmodifications have been suggested in the foregoing description, andothers will occur to those of ordinary skill in the art. Therefore, allsuch substitutions and modifications are intended to be embraced withinthe scope of the invention as defined in the appended claims.

1. A method for generating an input vector to reduce the leakage currentin an integrated circuit by using heuristics, said method comprising thesteps of: transforming said integrated circuit into a logicrepresentation with PMOS and NMOS parts, and P and N devices of saidintegrated circuit into edges; selecting between said PMOS and said NMOSlogic representations the one with deepest serial stack; and for saidselected PMOS or NMOS logic representation, assigning weights to saidedges in said selected PMOS or NMOS logic representation, therebygenerating a weighted graph, the weight assignment starting from theoutput terminal in said PMOS or NMOS logic representation to the PowerV_(dd) or Ground V_(ss) in said PMOS or NMOS logic representation, andweight assigned to each said edge being in a non-increasing order. 2.The method as claimed in claim 1, wherein said method further comprisesa step of applying a heuristics algorithm using said weighted graph togenerate said input vector for said integrated circuit.
 3. The method asclaimed in claim 1, wherein said integrated circuit is a CMOS circuit.4. The method as claimed in claim 2, wherein said heuristics algorithmis a branch-and-bound algorithm.
 5. The method as claimed in claim 2,wherein said heuristics algorithm is a simulated annealing algorithm. 6.The method as claimed in claim 2, wherein said heuristics algorithm is agenetic algorithm.
 7. The method as claimed in claim 1, wherein in saidselecting step, a depth-first search is performed to determine the depthof said PMOS and said NMOS logic representations.
 8. The method asclaimed in claim 7, wherein said PMOS logic representation is selectedfor weight assignment in said selecting step when said PMOS and saidNMOS logic representations have the same depth and a PMOS foundrytechnology provides a better leakage current control.
 9. The method asclaimed in claim 7, wherein said NMOS representation is selected forweight assignment in said selecting step when said PMOS and said NMOSlogic representations have the same depth and an NMOS foundry technologyprovides a better leakage current control.
 10. The method as claimed inclaim 1, wherein in said weight assignment step, a depth-first searchalgorithm is performed to assign weight to said edges.
 11. The method asclaimed in claim 1, wherein in said weight assignment step, abreadth-first search algorithm is performed to assign weight to saidedges.
 12. A method for generating an input vector to reduce the leakagecurrent in an integrated circuit by using heuristics, said methodcomprising the steps of: transforming said integrated circuit into alogic representation with PMOS and NMOS parts, and P and N devices ofsaid integrated circuit into edges; selecting between said PMOS and saidNMOS logic representations the one with deepest serial stack; for thesaid selected PMOS or NMOS logic representation, assigning weights tosaid edges in said selected PMOS or NMOS logic representation, therebygenerating a weighted graph, the weight assignment starting from theoutput terminal in said PMOS or NMOS logic representation to the powerV_(dd) or ground V_(ss) in said PMOS or NMOS logic representation, andweight assigned to each said edge being in a non-increasing order; andapplying a heuristics algorithm using said weighted graph to generatesaid input vector for said integrated circuit.
 13. The method as claimedin claim 12, wherein said integrated circuit is a CMOS circuit.
 14. Themethod as claimed in claim 12, wherein said heuristics algorithm is analgorithm chosen from one of branch-and-bound algorithm, simulatedannealing algorithm and genetic algorithm.
 15. The method as claimed inclaim 11, wherein in said selecting step, a depth-first search isperformed to determine the depth of said PMOS and said NMOS logicrepresentations.
 16. The method as claimed in claim 11, wherein saidPMOS logic representation is selected for weight assignment in saidselecting step, when said PMOS and said NMOS logic representations havethe same depth and a PMOS foundry technology provides a better leakagecurrent control.
 17. The method as claimed in claim 11, wherein saidNMOS logic representation is selected for weight assignment in saidselecting step, when said PMOS and said NMOS logic representations havethe same depth and an NMOS foundry technology provides a better leakagecurrent control.
 18. The method as claimed in claim 11, wherein in saidweight assignment step, a depth-first search algorithm is performed toassign weight to said edges.
 19. The method as claimed in claim 1,wherein in said weight assignment step, a breadth-first search algorithmis performed to assign weight to said edges.